1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device employing a inverter, and more specifically, to an inverter at an initial stage of input.
2. Description of the Background Art
A semiconductor integrated circuit device such as a semiconductor memory device and a microcomputer includes various logic circuits. These logic circuits have different operation voltages and different values of logic amplitude. For this reason, an inverter having wide operation margin is required as an inverter at the initial stage.
FIG. 5 is a block diagram showing an input portion of a dynamic random access memory (hereinafter referred to as a DRAM) for explaining the background of the invention. Referring to FIG. 5, the input portion of the DRAM includes external terminals ext. RAS, ext. CAS, ext. W, ext. Add, ext. R, Din and Vcc and a plurality of input buffer circuits 100.
A row address strobe signal is input through the external terminal ext. RAS.
A column address strobe signal is input through the external terminal ext. CAS.
A write control signal is input through the external terminal ext. W.
Row and column address signals for selecting a row and a column of the memory cell array, not shown, are input through the external terminal ext. Add.
External data is input through the external terminal Din.
The input buffer circuits 100 are connected to corresponding external terminals and convert the external signals to internal signals int. RAS, int. CAS, int. W, int. Add, int. R, and int. Din.
In operation, the input buffer circuit 100 detects an external signal input through the external terminal, and outputs an internal signal whose logical amplitude is limited by the supply voltage Vcc and the ground potential. In this manner, the internal signals are adapted to have sufficient level to drive or control the row decoder, column decoder, write/read control circuit (not shown) of the DRAM, enabling accessing operation of the DRAM.
In order to realize the aforementioned levels of the internal signals, a CMOS inverter such as shown in FIG. 6 is generally used.
FIG. 6 is a schematic diagram showing a semiconductor integrated circuit device employing a conventional CMOS inverter without taking into consideration the operation margin.
Referring to FIG. 6, the semiconductor integrated circuit device includes P channel transistors 1a and 4a, and N channel transistors 1b and 4b. P channel transistor 1a and N channel transistor 1b are complementarily connected to form a CMOS inverter. More specifically, the gate electrodes are commonly connected to an input node N1 to receive an input signal, and the drain electrodes are commonly connected to an output node N2. The source electrode of P channel transistor 1a is connected to the supply voltage Vcc, and the source electrode of N channel transistor 1b is connected to the ground potential. P channel transistor 4a and N channel transistor 4b are also complimentarily connected as in the case of P channel transistor 1a and N channel transistor 1b. The gate electrodes of P channel transistor 4a and N channel transistor 4b are commonly connected to an input node N3, and the drain electrodes are connected to an output node N4. The output node N4 is connected to a load of a succeeding stage.
In operation, when an input signal is at the "H" (high) level, P channel transistor 1a turns off, N channel transistor 1b turns on, and an output of "L" (low) level is provided from output node N2. In response, P channel transistor 4a of the next stage turns on, and N channel transistor 4b turns off. Consequently, an output of "H" level is provided from output node N4. On the other hand, when the input signal is at the "L" level, P channel transistor 1a turns on, N channel transistor 1b turns off, and an output of "H" level is provided from output node N2. In response, P channel transistor 4a of the next stage turns off, and N channel transistor 4b turns on. Thus an output of "L" level is provided from output node N4.
In the above described switching operation, the minimum voltage value (hereinafter referred to as V.sub.IH mind) enabling determination of the input signal as "H" level is determined dependent on the ratio of the sizes of P channel transistor 1a and N channel transistor 1b constituting the CMOS inverter of the initial stage. Therefore, V.sub.IH min generally depends on the supply voltage. As a result, the higher the supply voltage is, the higher V.sub.IH min becomes, and the smaller the margin becomes. It is determined as a specification that semiconductor integrated circuits operate normally in the range of .+-.10% of rated voltage Vcc=5 V.
The maximum voltage value (hereinafter referred to as V.sub.IL max) enabling determination of the input signal as "L" is similarly depends on the supply voltage Vcc. Therefore, the lower the supply voltage is, the smaller V.sub.IL max becomes, and the smaller the margin becomes.
As described above, the conventional semiconductor integrated circuit device has a problem that the margins of V.sub.IH min and V.sub.IL max become smaller dependent on variation of the supply voltage.
If the ratio of the sizes of P channel transistor 1a and N channel transistor 1b constituting the CMOS inverter is changed to enlarge the margin of V.sub.IH min, the margin of V.sub.IL max become smaller. On the contrary, if the margin for V.sub.IL max is to be enlarged, the margin for V.sub.IH min becomes smaller.
Thus, the operation margin cannot be sufficiently improved simply by changing the ratio of the sizes of P channel transistor and N channel transistor constituting the CMOS inverter.
If the operation margin is small and the input voltage includes noise, determination as to whether the input signal is at the high level or low level is delayed, which possibly causes malfunction in a semiconductor memory device or in a digital semiconductor integrated circuit such as a micro-computer.